1. Field of the Invention
The present invention relates to the fabrication of integrated circuits on semiconductor wafers, and in particular to a system capable of monitoring a plurality of performance characteristics of wafer carriers and to a system for managing carrier operation on a fab-wide basis.
2. Description of Related Art
A SMIF system proposed by the Hewlett-Packard Company is disclosed in U.S. Pat. Nos. 4,532,970 and 4,534,389. The purpose of a SMIF system is to reduce particle fluxes onto semiconductor wafers during storage and transport of the wafers through the semiconductor fabrication process. This purpose is accomplished, in part, by mechanically ensuring that during storage and transport, the gaseous media (such as air or nitrogen) surrounding the wafers is essentially stationary relative to the wafers, and by ensuring that particles from the ambient environment do not enter the immediate wafer environment.
A SMIF system has three main components: (1) minimum volume, sealed carriers, or pods, used for storing and transporting wafers and/or wafer cassettes; (2) an input/output (I/O) minienvironment located on a semiconductor processing tool to provide a miniature clean space (upon being filled with clean air) in which exposed wafers and/or wafer cassettes may be transferred to and from the interior of the processing tool; and (3) an interface for transferring the wafers and/or wafer cassettes between the SMIF carriers and the SMIF minienvironment without exposure of the wafers or cassettes to particulates. Further details of one proposed SMIF system are described in the paper entitled xe2x80x9cSMIF: A TECHNOLOGY FOR WAFER CASSETTE TRANSFER IN VLSI MANUFACTURING,xe2x80x9d by Mihir Parikh and Ulrich Kaempf, Solid State Technology, July 1984, pp. 111-115.
Systems of the above type are concerned with particle sizes which range from below 0.02 microns (xcexcm) to above 200 xcexcm. Particles with these sizes can be very damaging in semiconductor processing because of the small geometries employed in fabricating semiconductor devices. Typical advanced semiconductor processes today employ geometries which are one-half xcexcm and under. Unwanted contamination particles which have geometries measuring greater than 0.1 xcexcm substantially interfere with 1 xcexcm geometry semiconductor devices. The trend, of course, is to have smaller and smaller semiconductor processing geometries which today in research and development labs approach 0.1 xcexcm and below. In the future, geometries will become smaller and smaller and hence smaller and smaller contamination particles and molecular contaminants become of interest.
SMIF carriers are in general comprised of a carrier door which mates with a carrier shell to provide a sealed environment in which wafers may be stored and transferred. So called xe2x80x9cbottom openingxe2x80x9d carriers are known, where the carrier door is horizontally provided at the bottom of the carrier, and the wafers are supported in a cassette which is in turn supported on the carrier door. It is also known to provide xe2x80x9cfront openingxe2x80x9d carriers, in which the carrier door is located in a vertical plane, and the wafers are supported either in a cassette mounted within the carrier shell, or to shelves mounted in the carrier shell.
A typical wafer fab has several different types of tools into which wafers from a carrier are loaded. Processing tools are used to form patterned layers of silicon, silicon compounds and metals on the wafer to define the individual IC devices. Metrology tools are used for performing various tests on wafers to ensure the wafers are fabricated to specification. Carrier cleaning tools are used to periodically clean the interior surfaces of a carrier to remove particulates and contaminants that accumulate within a carrier with use. Another tool found in a wafer fab is a sorter, which performs various functions including the transfer of wafers between the various carriers positioned on the wafer sorter, the mapping of wafer location within a carrier cassette, and wafer identification.
In order to transfer wafers between a SMIF carrier and the various tools within a wafer fab, a carrier is typically loaded either manually or automatedly onto a load port assembly on a front of the tool. Each load port assembly includes an access port which, in the absence of a carrier, is covered by a port door. The SMIF carrier is seated on the load port so that the carrier door and port door lie juxtaposed to each other. In a front opening system, the carrier is seated on a carrier advance plate which advances the carrier to the port so that the respective carrier and port doors lie adjacent to each other. Registration pins are provided on the port door that mate with grooves in the carrier door to assure a proper alignment of the carrier door with respect to the port door.
Once the carrier is positioned against the port door, mechanisms within the port door unlatch the carrier door from the carrier shell and move the carrier door and port door together into the process tool where the doors are then stowed away from the wafer transfer path. The carrier shell remains in proximity to the interface port so as to maintain a clean environment including the interior of the process tool and the carrier shell around the wafers. A wafer handling robot within the process tool may thereafter access particular wafers supported in the carrier for transfer between the carrier and the process tool.
Wafer carriers are manufactured to relatively narrow tolerances and are tested prior to initial use within a wafer fab to ensure they have been manufactured to specifications. However, carriers are subject to wear, deformation, breakage and improper maintenance in use, and several performance characteristics of each carrier should be monitored over the life of the carrier as it transports various wafer lots around the fab. These performance characteristics which should be monitored include the following:
Seal Performance
One or more elastomeric seals are provided between the carrier shell and the carrier door to prevent fluids from traveling into or out of the carrier when the door is sealed within the shell. These elastomeric seals wear over time and gradually become less effective in isolating the environment within the carrier from the environment surrounding the carrier.
Seal performance refers to how effective an elastomeric seal in a carrier is at a given point in the life of a carrier at preventing fluid flow around the seal between the carrier shell and carrier door.
Cleanliness
Cleanliness relates to the amount of contaminants found within a carrier at a given time. Contaminants may be grouped into two classes, and there are different removal and monitoring systems for each. The first type of contaminant includes relatively large particles, for example bigger than 0.02xcexc, which adhere to surfaces within the carrier. These particles are generally removed by injecting a cleaning solution onto the surfaces of the carrier to flush away the particles. A second type of contaminant relates to relatively small particles, for example smaller than 0.02xcexc. These particles may be airborne or adhered to surfaces. Such smaller particles may be removed by including a particle filter within the carrier, which removes particles that come into contact with the filter as they float around the interior of the carrier. These small particle contaminants are also removed from surfaces by the cleaning solution injected into the carrier.
Sources of contaminants within a carrier include worn elastomeric seals in a wafer carrier, fluids injected into the carrier and instances where the carrier is opened for maintenance or other purposes. As indicated above, it is important to monitor the cleanliness of the interior of a carrier, as particles can interfere with the device geometries formed on the wafers.
Relative Humidity
Wafer carriers are formed of various materials including plastics such as polycarbonate which absorb moisture. Thus, after a carrier is cleaned with a wet cleaning solution, it is common for the carrier to have a higher relative humidity than ambient for days after the cleaning. Humidity within a carrier can be a significant source of damage to a semiconductor wafer.
Wafer Height
It is important that wafers within a carrier be located at a known elevation relative to the load port and tool on which the carrier is loaded so that a wafer handling robot can cleanly lift a wafer off of a particular shelf and return a wafer to a particular shelf without unintended contact with the wafer. However, over time, factors such as carrier deformation, damage during use, improper maintenance and/or being manufactured outside of specifications can alter the height at which the shelves in the carrier are positioned relative to the load port. It is therefore desirable to check the position of the wafer support shelves within a carrier when a carrier is loaded onto a load port.
Carrier Latching Force
In a front opening interface, in order to couple a carrier door and carrier shell together, a mechanism in the port door rotates a pair of hubs in the carrier door, which in turn cause latch plates to extend into slots in the carrier shell. The latch plates also exert a force on the carrier shell so that the carrier door and shell are pulled tightly together. The same is true for bottom opening systems, but such systems typically include a single, central hub.
Front opening carriers further include a spring loaded mechanism for biasing wafers toward a rear of the carrier (i.e., away from the carrier door). Lying in contact with the edges of the wafers within the carrier, the spring loaded mechanism exerts an approximate 40 newton force against the carrier door. This force in turn generates an additional force by the latch plates against the carrier shell.
The force between the latch plates and carrier shell, and consequently the torque required to rotate the hubs in order to actuate the latch plates, can vary over time. It is important to monitor this force, as significant variations can affect the ability of the port door to couple and uncouple the carrier door and shell.
Electrostatic Neutralization
Electrostatic build up on and discharge from wafers can damage or destroy the wafers. Concern over electrostatic damage has been increasing in recent years as device geometries get finer and the requirements for reliability become more stringent. In conventional carriers, it is known to provide a conductive path away from the top and/or bottom surface of the wafer to neutralize electrostatic charge on the wafers. Conductive coatings provided for neutralizing the static charge may wear over time. Moreover, carriers may break, or a conductive pathway may be broken if a carrier is reassembled incorrectly during maintenance. It is therefore desirable to monitor the ability of a carrier to neutralize static electric charge.
Carrier Configuration Detector
A bottom surface of a carrier is generally provided with four designated positions at which wells may be formed. Similarly, the surface supporting a carrier at a load port assembly includes four corresponding positions at which pins may be provided. These wells on the bottom of a carrier can be used to define the type of carrier and/or the type of process for which the carrier is intended. For example, wafer fabs are often broken down into zones for different fabrication processes, and carriers for one zone should not be used in other zones. In this instance, wells could be provided in the various positions on the bottom of the carrier to designate a carrier for a particular zone. In practice, where a carrier is used in a proper zone, the well(s) on the bottom of the carrier match up with the pin(s) on the load port, and the carrier seats properly on the load port. On the other hand, where a carrier designated for one zone is used in another, incompatible zone, the well(s) in the bottom of the carrier would not match up with the pin(s) on the load port, and the carrier would not seat properly on the load port.
The well(s) on the bottom of a carrier can be used to designate and distinguish a carrier between a variety of other classifications, such as for example designating a carrier as a 25 wafer carrier versus a 13 wafer carrier; an enclosed SMIF carrier versus an open cassette; a carrier supporting 300 mm wafers versus a carrier supporting 200 mm wafers, etc. In each instance, the pins on a load port will ensure that a carrier will only seat on a load port which is designated to receive that type of carrier.
It is also known to provide a sensor within a well which generates a signal when a pin seats within that well. Such a system provides feedback as to whether the sensors on the bottom of a carrier in fact match up with pins on the load port assembly. This system provides an additional advantage that the sensors can distinguish between a greater number of pin configurations on a load port, and hence a greater number of different carrier configurations and processes, than can the wells by themselves.
It would be advantageous to monitor situations where a carrier is placed on a compatible load port and situations where a carrier is placed on an incompatible load port, as well as the frequency of both situations.
In addition to collecting data with regard to each of the above-described performance characteristics of the carrier, it would be useful to accumulate and analyze this data to improve and optimize management of carrier operations throughout the wafer fab. For example, this data could be used to analyze how various performance characteristics of the carrier population change overtime. This data can then be used to manage and maintain the carrier population in an efficient manner, and also identify when a carrier needs to be replaced.
It is therefore an advantage of the present invention to provide a smart load port for capturing data relating to a plurality of carrier and load port performance characteristics.
It is a further advantage of the present invention to store the data on a central server for use in managing carrier operation within the wafer fab.
It is a further advantage of the present invention to measure several performance characteristics without impacting throughput of wafers on a tool.
It is a further advantage of the present invention to ensure that carriers are being cleaned properly and with the proper frequency.
It is another advantage of the present invention to provide a system which identifies when carrier seals begin to fail and when the seals need to be replaced.
It is a further advantage of the present invention to identify the relative humidity within a carrier at a given time and to determine how carriers dry over time.
It is a further advantage of the present invention to provide physical information pads to prevent location of a carrier designated for one type of process on a load port for performing another, incompatible process.
It is a still further advantage of the present invention to ensure that wafer heights are within standard specifications.
These and other advantages are provided by the present invention which in preferred embodiments relates to a system capable of monitoring a plurality of performance characteristics of a wafer carrier on a load port, and to a system for managing carrier operation on a fab-wide basis. In particular, several detector and measurement systems are built into or associated with the load port assembly. These detector and measurement systems include a torque measurement system, a wafer height measurement system, a carrier identification reader, an information pad, a resistivity measurement system, a cleanliness measurement system, a seal performance detector and a relative humidity detector. These monitoring systems can be provided on load ports associated with various tools, such as processing tools, metrology tools, carrier cleaning tools and sorters, to gather data relating to individual carriers and the carrier population as a whole.
In accordance with further principals of the present invention, the data gathered by the various measuring and detecting systems within the load port assembly can be used to manage the carrier population within the fab. For example, by monitoring a performance characteristic over time, across the entire carrier population in the wafer fab, the average change in that performance characteristic over time may be accurately mapped for the population in general. The standard deviation for the carrier population with respect to that performance characteristic over time may also be determined and stored.
This stored information can be used to provide valuable forecasting information, which may be printed in report form, as to when the average carrier or carrier subsystem would generally require maintenance or replacement. This information can also be used to identify carriers which are broken, have failed, or which are performing outside of acceptable ranges for carriers of comparable age. Moreover, the entire history of a carrier, for each of the performance characteristics, can be stored. This promotes optimal carrier management efficiency in that the optimal average timing for maintenance and/or replacement of carriers is known. Moreover, defective carriers may be quickly identified and removed from the carrier population.